Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

32072H–AVR32–10/2012

The size field is encoded as i 

.

Starting in Run-Test/Idle, SAB data is accessed in the following way:

1.

Select the IR Scan path.

2.

In Capture-IR: The IR output value is latched into the shift register.

3.

In Shift-IR: The instruction register is shifted by the TCK input.

4.

Return to Run-Test/Idle.

5.

Select the DR Scan path.

6.

In Shift-DR: Scan in the direction bit (1=read, 0=write), 2-bit access size, and the 36-bit 
address of the data to access.

7.

Go to Update-DR and re-enter Select-DR Scan.

8.

In Shift-DR: For a read operation, scan out the contents of the addressed area. For a 
write operation, scan in the new contents of the area.

9.

Return to Run-Test/Idle.

For any operation, the full 36 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.

Table 35-18. Size Field Semantics

00

Byte (8 bits)

Address modulo 4 : data alignment

0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx

1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx

2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx

3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd

01

Halfword (16 bits)

Address modulo 4 : data alignment

0: dddddddd dddddddd xxxxxxxx xxxxxxxx

1: Not allowed

2: xxxxxxxx xxxxxxxx dddddddd dddddddd

3: Not allowed

10

Word (32 bits)

Address modulo 4 : data alignment

0: dddddddd dddddddd dddddddd dddddddd

1: Not allowed

2: Not allowed

3: Not allowed

11

Reserved

N/A

Table 35-19. MEMORY_SIZED_ACCESS Details

IR input value

10101 (0x15)

IR output value

peb01

DR Size

39 bits

DR input value (Address phase)

aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr

DR input value (Data read phase)

xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx

DR input value (Data write phase)

dddddddd dddddddd dddddddd dddddddd xxxxxxx