Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet

Product codes
AT32UC3A3-XPLD
Page of 1021
973
32072H–AVR32–10/2012
AT32UC3A3
36.8.3
Main Oscillators
36.8.4
Phase Lock Loop (PLL0, PLL1)
36.8.5
USB Hi-Speed Phase Lock Loop
Table 36-19. Main Oscillators Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
1/(t
CPMAIN
)
Oscillator Frequency
External clock on XIN
50
MHz
Crystal
0.4
20
MHz
C
L1
, C
L2
Internal Load Capacitance (C
L1
 = C
L2
)
7
pF
ESR
Crystal Equivalent Series Resistance
75
Ω
Duty  Cycle
40
50
60
%
t
ST
Startup Time
f = 400 KHz
f = 8 MHz
f = 16 MHz
f = 20 MHz
25
4
1.4
1
ms
t
CH
XIN Clock High Half-period
0.4 t
CP
0.6 t
CP
t
CL
XIN Clock Low Half-period
0.4 t
CP
0.6 t
CP
C
IN
XIN Input Capacitance
7
pF
I
OSC
Current Consumption
Active mode at 400 KHz. Gain = G0
Active mode at 8 MHz. Gain = G1
Active mode at 16 MHz. Gain = G2
Active mode at 20 MHz. Gain = G3
30
45
95
205
µA
Table 36-20. PLL Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
F
OUT
VCO Output Frequency
80
240
MHz
F
IN
Input Frequency (after input divider)
4
16
MHz
I
PLL
Current Consumption
Active mode (Fout=80 MHz)
250
µA
Active mode (Fout=240 MHz)
600
µA
Table 36-21. PLL Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
F
OUT
VCO Output Frequency
480
MHz
F
IN
Input Frequency 
12
MHz
Delta F
IN
Input Frequency Accuracy (applicable 
to Clock signal on XIN or to Quartz 
tolerance)
-500
+500
ppm
I
PLL
Current Consumption
Active mode @480MHz @1.8V
2.5
mA