Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Data Sheet
Product codes
AT32UC3A3-XPLD
981
32072H–AVR32–10/2012
AT32UC3A3
SDRAMC
13
Bank Change before SDCK Rising Edge
6.3
ns
SDRAMC
14
Bank Change after SDCK Rising Edge
2.4
ns
SDRAMC
15
CAS Low before SDCK Rising Edge
7.4
ns
SDRAMC
16
CAS High after SDCK Rising Edge
1.9
ns
SDRAMC
17
DQM Change before SDCK Rising Edge
6.4
ns
SDRAMC
18
DQM Change after SDCK Rising Edge
2.2
ns
SDRAMC
19
D0-D15 in Setup before SDCK Rising Edge
9
ns
SDRAMC
20
D0-D15 in Hold after SDCK Rising Edge
0
ns
SDRAMC
23
SDWE Low before SDCK Rising Edge
7.6
ns
SDRAMC
24
SDWE High after SDCK Rising Edge
1.8
ns
SDRAMC
25
D0-D15 Out Valid before SDCK Rising Edge
7.1
ns
SDRAMC
26
D0-D15 Out Valid after SDCK Rising Edge
1.5
ns
Table 36-36. SDRAM Clock Signal
Symbol
Parameter
Conditions
Min.
Max.
Unit