Linear Technology LTC4265 IEEE802.3at PD Controller DC1415A DC1415A Data Sheet
Product codes
DC1415A
LTC4265
3
4265fa
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltages are with respect to V
IN
pin unless otherwise noted.
Note 3: Pins with 100V absolute maximum guaranteed for T ≥ 0ºC, otherwise 90V.
Note 4: PWRGD voltage clamps at 14V with respect to V
OUT
.
Note 5: Input voltage specifi cations are defi ned with respect to LTC4265
pins and meet IEEE 802.3af/at specifi cations when the input diode bridge
is included.
pins and meet IEEE 802.3af/at specifi cations when the input diode bridge
is included.
The
l
denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
A
= 25°C.
Note 6: Signature resistance is measured via the
ΔV/ΔI method with a
minimum
ΔV of 1V. The LTC4265 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 7: An invalid signature after the 1st classifi cation event is mandated
by IEEE 802.3at standard. See Applications Information.
by IEEE 802.3at standard. See Applications Information.
Note 8: Class accuracy is with respect to the ideal current defi ned as
1.237/R
1.237/R
CLASS
and does not include variations in R
CLASS
resistance.
Note 9: This parameter is assured by design and wafer level testing.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input Voltage
Signature
Signature
Range
Classifi cation Range
Turn-On
Voltage
Undervoltage Lock Out
Overvoltage Lock Out
At GND Pin (Note 5)
l
l
l
l
1.5
12.5
30.0
71
60
9.8
21
37.2
V
V
V
V
V
V
V
V
V
V
V
ON/UVLO Hysteresis Window
l
4.1
V
Signature/Class Hysteresis Window
l
1.4
V
Reset Threshold
State Machine Reset for 2-event Classifi cation
l
2.57
5.40
V
SUPPLY CURRENT
Supply Current at 60V
Measured at GND Pin
l
1.35
mA
Class 0 Current
GND = 17.5V, No R
CLASS
Resistor
l
0.40
mA
SIGNATURE
Signature Resistance
1.5V ≤ GND ≤ 9.8V (Note 6)
l
23.25
26
kΩ
Invalid Signature Resistance, SHDN Invoked
1.5V ≤ GND ≤ 9.8V, V
SHDN
= 3V (Note 6)
l
11
kΩ
Invalid Signature Resistance During Mark Event (Notes 6, 7)
l
11
kΩ
CLASSIFICATION
Class Accuracy
10mA < I
CLASS
< 40mA, 12.5V < GND < 21V (Note 8, 9)
l
±3.5
%
Classifi cation Stability Time
GND Pin Step to 17.5V, R
CLASS
= 30.9, I
CLASS
Within
3.5% of Ideal Value (Notes 8, 9)
l
1
ms
NORMAL OPERATION
Inrush Current
GND = 54, V
OUT
= 3V
l
60
100
180
mA
Power FET On Resistance
Tested at 600mA into V
OUT
, GND = 54V
l
0.70
1.0
Ω
Power FET Leakage Current at V
OUT
GND = SHDN = V
OUT
= 57V
l
1
μA
DIGITAL INTERFACE
SHDN Input High Level Voltage
l
3
V
SHDN Input Low Level Voltage
l
0.45
V
SHDN Input Resistance
GND = 9.8V, SHDN = 9.65V
l
100
kΩ
PWRGD, T2PSE Voltage Output Low
Tested at 1mA, GND = 54V. For T2PSE, Must Complete
2-event Classifi cation to See Active Low.
2-event Classifi cation to See Active Low.
l
0.15
V
PWRGD, T2PSE Leakage Current
Pin Voltage Pulled 57V, GND = V
IN
= 0
l
1
μA
PWRGD Voltage Output Low
Tested at 0.5mA, GND = 52V, V
OUT
= 48V, Output Voltage
is with Respect to V
OUT
l
0.4
V
PWRGD Voltage Clamp
Tested at 2mA, V
OUT
= 0V, Voltage with Respect to V
OUT
l
12
16.5
V
PWRGD Leakage Current
V
PWRGD
= 11V, V
OUT
= V
IN
= 0V, GND = 54V
l
1
μA