Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
397
AT32UC3A
27.6.7.4
NWAIT Latency and Read/write Timings
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1
cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT
.
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the
read and write controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
Figure 27-31.
NWAIT Latency
Wait STATE
0
1
2
3
4
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
NRD
NWAIT
nternally synchronized
NWAIT signal
Minimal pulse length
0
0
NWAIT latency 2 cycle resynchronization
Read cycle
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
32058K
AVR32-01/12