Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
527
AT32UC3A
Figure 30-27.
Example of an OUT Pipe with 1 Data Bank
Figure 30-28.
Example of an OUT Pipe with 2 Data Banks and no Bank Switching Delay
Figure 30-29.
Example of an OUT Pipe with 2 Data Banks and a Bank Switching Delay
30.7.3.12
CRC Error
This error exists only for isochronous IN pipes. It raises the CRC Error interrupt (CRCERRI),
what triggers a PXINT interrupt if CRCERRE = 1.
A CRC error can occur during IN stage if the USB controller detects a corrupted received packet.
A CRC error can occur during IN stage if the USB controller detects a corrupted received packet.
The IN packet is stored in the bank as if no CRC error had occurred (RXINI is raised).
OUT
DATA
(bank 0)
ACK
TXOUTI
FIFOCON
HW
write data to CPU
BANK 0
SW
SW
SW
SW
OUT
write data to CPU
BANK 0
OUT
DATA
(bank 0) ACK
TXOUTI
FIFOCON
write data to CPU
BANK 0
SW
SW
SW
SW
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
OUT
DATA
(bank 1) ACK
OUT
DATA
(bank 0)
ACK
TXOUTI
FIFOCON
write data to CPU
BANK 0
SW
SW
SW
SW
OUT
DATA
(bank 1)
ACK
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
32058K
AVR32-01/12