Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
678
AT32UC3A
- If the waveform is left aligned, then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
• the
waveform duty cycle
. This channel parameter is defined in the CDTY field of the CDTYx
register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
• the
waveform polarity.
At the beginning of the period, the signal can be at high or low level.
This property is defined in the CPOL field of the CMRx register. By default the signal starts by
a low level.
• the
waveform alignment
. The output waveform can be left or center aligned. Center aligned
waveforms can be used to generate non overlapped waveforms. This property is defined in the
CALG field of the CMRx register. The default mode is left aligned.
X
CPRD
×
(
)
MCK
-------------------------------
CRPD
DIVA
×
(
)
MCK
------------------------------------------
CRPD
DIVAB
×
(
)
MCK
----------------------------------------------
2 X CPRD
×
×
(
)
MCK
------------------------------------------
2 CPRD DIVA
×
×
(
)
MCK
-----------------------------------------------------
2 CPRD
×
DIVB
×
(
)
MCK
-----------------------------------------------------
duty cycle
period
1 fchannel_x_clock CDTY
×
⁄
–
(
)
period
---------------------------------------------------------------------------------------------------------
=
duty cycle
period
2
⁄
(
)
1 fchannel_x_clock CDTY
×
⁄
–
(
) )
period
2
⁄
(
)
------------------------------------------------------------------------------------------------------------------------
=
32058K
AVR32-01/12