Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105 Data Sheet
Product codes
ATEVK1105
741
AT32UC3A
36. JTAG and Boundary Scan
Rev.: 2.0.0.2
36.1
Features
•
IEEE1149.1 compliant JTAG Interface
•
Boundary-Scan Chain for board-level testing
•
Direct memory access and programming capabilities through JTAG interface
•
On-Chip Debug access in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0)
36.2
Overview
shows how the JTAG is connected in an AVR32 device. The TAP Con-
troller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects
either the JTAG Instruction Register or one of several Data Registers as the scan chain (shift
register) between the TDI-input and TDO-output. The Instruction Register holds JTAG instruc-
tions controlling the behavior of a Data Register.
The ID Register, Bypass Register, and the Boundary-Scan Chain are the Data Registers used
The ID Register, Bypass Register, and the Boundary-Scan Chain are the Data Registers used
for board-level testing. The Reset Register can be used to keep the device reset during test or
programming.
The Service Access Bus (SAB) interface contains address and data registers for the Service
The Service Access Bus (SAB) interface contains address and data registers for the Service
Access Bus, which gives access to on-chip debug, programming, and other functions in the
device. The SAB offers several modes of access to the address and data registers, as dis-
cussed in
lists the supported JTAG instructions, with references to the description in this
document.
32058K
AVR32-01/12