Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an 

EPnINT interrupt if RXOUTE is one.

This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full. 

This triggers an EPnINT interrupt if RXOUTE is one.

This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.

This bit is cleared when the TXINIC bit is written to one, acknowledging the interrupt. For control endpoints, this will send the 

packet. For other endpoint types, the user should clear the FIFOCON to allow the USBC to send the data. TXINI shall always be 

cleared before clearing FIFOCON to avoid missing an interrupt.

This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers an EPnINT interrupt 

if TXINE is one.

This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON when the current bank is free. 

This triggers an EPnINT interrupt if TXINE is one.

This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.