Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

Product codes
ATSAM4L-EK
Page of 1204
607
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 24-40. Master Node with Peripheral DMA Controller (LINMR.PDCM=0)
Figure 24-41. Master Node with Peripheral DMA Controller (LINMR.PDCM=1)
24.6.12.2
Slave Node Configuration
In this mode, the Peripheral DMA Controller transfers only data. The user reads the Identifier
from LINIR, and selects LIN mode by writing to LINMR. When NACT=PUBLISH the data is in the
write buffer, while the read buffer contains the data when NACT=SUBSCRIBE.
IMPORTANT: If in slave mode, LINMR.NACT is already configured correctly as PUBLISH, the
LINMR register must still be written with this value in order to set CSR.TXRDY, and to request
the corresponding Peripheral DMA Controller write transfer.
|
|
|
|
RXRDY
TXRDY
Peripheral 
bus
USART LIN 
CONTROLLER
DATA 0
DATA N
|
|
|
|
READ BUFFER
NODE ACTION = PUBLISH
NODE ACTION = SUBSCRIBE
Peripheral DMA 
Controller
RXRDY
Peripheral 
bus
DATA 0
DATA 1
DATA N
WRITE BUFFER
Peripheral DMA 
Controller
USART LIN 
CONTROLLER
|
|
|
|
|
|
|
|
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
RXRDY
Peripheral 
bus
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
RXRDY
READ BUFFER
NODE ACTION = PUBLISH
NODE ACTION = SUBSCRIBE
Peripheral DMA 
Controller
Peripheral DMA 
Controller
USART LIN 
CONTROLLER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
USART LIN 
CONTROLLER
TXRDY
Peripheral 
bus