Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet

42023E–SAM–07/2013

If the WDT Mode (MODE) bit in the CTRL Register is one, the WDT is in window mode. Note
that the CTRL.MODE bit can only be changed when the WDT is disabled (CTRL.EN=0).

The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT
timeout period

T

timeout

 = T

tban

 + T

psel

 = (2

(TBAN+1)

 + 2

(PSEL+1)

) / f

clk_cnt

where T

tban

 sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR

bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the
code will start executing form the boot vector, see 

. The WDT counter

will be cleared.

Writing a one to the CLR.WDTCLR bit within the T

psel

 period will clear the WDT counter and the

counter starts counting from zero (t=t

0

), entering T

tban

, see 

If the value in the CTRL Register is changed, the WDT counter will be cleared without a watch-
dog reset, regardless of if the value in the WDT counter and the TBAN value.

If the WDT counter reaches T

timeout

, the counter will be cleared, the device will receive a reset

and the code will start executing form the boot vector.

Figure 20-4. Window Mode WDT Timing Diagram

T

tban

T

psel

Timeout

Write one to 

CLR.WDTCLR

Watchdog reset

t=t

0