Linear Technology LTC4353DE Demoboard, Dual Low Voltage Ideal Diode Controller DC1926A DC1926A Data Sheet
Product codes
DC1926A
LTC4353
3
4353f
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supplies
V
V
IN
V
IN1
, V
IN2
Operating Range
With External V
CC
Supply
l
l
2.9
0
18
V
CC
V
V
V
CC(EXT)
V
CC
External Supply Operating Range
V
IN1
, V
IN2
≤ V
CC
l
2.9
6
V
V
CC(REG)
V
CC
Regulated Voltage
l
4.5
5
5.5
V
I
IN
V
IN1
, V
IN2
Current
Enabled, Higher Supply
Enabled, Lower Supply
Pull-Up
Disabled
Other V
IN
= 11.7V, Both EN = 0V
Other V
IN
= 12.3V, Both EN = 0V
Both V
IN
= 0V, V
CC
= 5V, Both EN = 0V
Both EN = 1V
l
l
l
l
1.5
200
–45
75
2.5
300
–80
160
mA
µA
µA
µA
I
CC
V
CC
Current
Enabled
Disabled
V
CC
= 5V, Both V
IN
= 1.2V, Both EN = 0V
V
CC
= 5V, Both V
IN
= 1.2V, Both EN = 1V
l
l
1.5
88
2.2
190
mA
µA
V
CC(UVLO)
V
CC
Undervoltage Lockout Threshold
V
CC
Rising
l
2.3
2.55
2.7
V
ΔV
CC(HYST)
V
CC
Undervoltage Lockout Hysteresis
l
40
120
300
mV
Ideal Diode Control
V
V
FR
Forward Regulation Voltage (V
IN
− OUT)
V
IN
= 1.2V, V
CC
= 5V
V
IN
= 12V
l
l
2
2
12
25
25
50
mV
mV
ΔV
GATE
MOSFET Gate Drive (GATE – V
IN
)
V
FWD
= 0.2V; I = 0, −1μA; Highest V
IN
=12V
V
FWD
= 0.2V; I = 0, −1μA; Highest V
IN
=2.9V
l
l
10
4.5
12
7
14
9
V
V
t
ON(GATE)
GATE1, GATE2 Turn-On Propagation Delay
V
FWD
(= V
IN
– OUT) Step: −0.3V to 0.3V
l
0.4
1
µs
t
OFF(GATE)
GATE1, GATE2 Turn-Off Propagation Delay
V
FWD
Step: 0.3V to −0.3V
l
0.3
1
µs
I
GATE
GATE1, GATE2 Fast Pull-Up Current
GATE1, GATE2 Fast Pull-Down Current
GATE1, GATE2 Off Pull-Down Current
V
FWD
= 0.4V, ΔV
GATE
= 0V, CPO = 17V
V
FWD
= −0.8V, ΔV
GATE
= 5V
Corresponding EN = 1V, ΔV
GATE
= 2.5V
l
l
l
–0.9
0.9
65
–1.4
1.4
110
–1.9
1.9
160
A
A
µA
Input/Output Pins
V
V
EN(TH)
EN1, EN2 Threshold Voltage
EN Falling
l
580
600
620
mV
ΔV
EN(TH)
EN1, EN2 Threshold Hysteresis
l
2
8
20
mV
I
EN
EN1, EN2 Current
At 0.6V
l
0
±1
µA
I
OUT
OUT1, OUT2 Current
Enabled
Disabled
OUT
n = 0V, 12V; Both EN = 0V
Both EN = 1V
l
l
–4
8
160
16
µA
µA
I
CPO(UP)
CPO1, CPO2 Pull-Up Current
CPO = V
IN
l
–40
–70
–115
µA
V
OL
ONST1, ONST2 Output Low Voltage
I = 1mA
I = 3mA
l
l
0.14
0.42
0.4
1.2
V
V
V
OH
ONST1, ONST2 Output High Voltage
I = −1μA
l
V
CC
– 1.4 V
CC
– 0.9 V
CC
– 0.5
V
I
ONST
ONST1, ONST2 Leakage Current
At 12V
l
0
±1
µA
ΔV
GATE(ON)
MOSFET On-Detect Threshold (GATE – V
IN
) ONST Pulls Low
l
0.28
0.7
1.1
V
The
l
denotes those specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
IN1
= V
IN2
= 12V, OUT = V
IN
, V
CC
Open, unless otherwise noted.
Note 3: Internal clamps limit the GATE and CPO pins to a minimum of 10V
above, and a diode below the corresponding V
IN
pin. Driving these pins to
voltages beyond the clamp may damage the device.