Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
149
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
When the FDPLL96M is disabled, the output clock is reset. If the loop divider ratio fractional part
(DPLLRATIO.LDRFRAC) field is reset, the FDPLL96M works in integer mode, otherwise the fractional mode is activated.
It shall be noted that fractional part has a negative impact on the jitter of the FDPLL96M.
(DPLLRATIO.LDRFRAC) field is reset, the FDPLL96M works in integer mode, otherwise the fractional mode is activated.
It shall be noted that fractional part has a negative impact on the jitter of the FDPLL96M.
Example (integer mode only): assuming f
ckr
= 32kHz and f
ck
= 48MHz, the multiplication ratio is 1500. It means that LDR
shall be set to 1499.
Example (fractional mode): assuming f
ckr
= 32 kHz and f
ck
= 48.006MHz, the multiplication ratio is 1500.1875 (1500 +
3/16). Thus LDR is set to 1499 and LDRFRAC to 3.
16.6.8.4 Initialization, Enabling, Disabling and Resetting
The FDPLL96M is enabled by writing a one to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The
FDPLL96M is disabled by writing a zero to DPLLCTRLA.ENABLE. The frequency of the FDPLL96M output clock CK is
stable when the module is enabled and when the DPLL Lock Status bit in the DPLL Status register
(DPLLSTATUS.LOCK) bit is set. When DPLLCTRLB.LTIME is different from 0, a user defined lock time is used to
validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME is reset, the lock signal is linked
with the status bit of the DPLL, the lock time vary depending on the filter selection and final target frequency.
FDPLL96M is disabled by writing a zero to DPLLCTRLA.ENABLE. The frequency of the FDPLL96M output clock CK is
stable when the module is enabled and when the DPLL Lock Status bit in the DPLL Status register
(DPLLSTATUS.LOCK) bit is set. When DPLLCTRLB.LTIME is different from 0, a user defined lock time is used to
validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME is reset, the lock signal is linked
with the status bit of the DPLL, the lock time vary depending on the filter selection and final target frequency.
When DPLLCTRLB.WUF is set, the wake up fast mode is activated. In that mode the clock gating cell is enabled at the
end of the startup time. At that time, the final frequency is not stable as it is still in the acquisition period, but it allows to
save several milliseconds. After first acquisition, DPLLCTRLB.LBYPASS indicates if the Lock signal is discarded from
the control of the clock gater generating the output clock CLK_FDPLL96M.
end of the startup time. At that time, the final frequency is not stable as it is still in the acquisition period, but it allows to
save several milliseconds. After first acquisition, DPLLCTRLB.LBYPASS indicates if the Lock signal is discarded from
the control of the clock gater generating the output clock CLK_FDPLL96M.
f
clk_fdpll96m_ref
f
xosc
1
2
DIV 1
+
(
)
×
----------------------------------
⎝
⎠
⎛
⎞
×
=
Table 16-4. CLK_FDPLL96M behavior from startup to first edge detection.
WUF
LTIME
CLK_FDPLL96M Behavior
0
0
Normal Mode: First Edge when lock is asserted
0
Not Equal To Zero
Lock Timer Timeout mode: First Edge when the timer downcounts to 0.
1
X
Wake Up Fast Mode: First Edge when CK is active (startup time)
Table 16-5. CLK_FDPLL96M behavior after First Edge detection.
LBYPASS
CLK_FDPLL96M Behavior
0
Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1
Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.