Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

measured voltage, the following formula can be used:

To enable the temperature sensor, write a one the Temperature Sensor Enable bit (VREF.TSEN) in the VREF register.

The temperature sensor can be redirected to the ADC for conversion. The Bandgap Reference Voltage Generator output 
can also be routed to the ADC if the Bandgap Output Enable bit (VREF.BGOUTEN) in the VREF register is set.

The Bandgap Reference Voltage Generator output level is determined by the CALIB bit group (VREF.CALIB) value in the 
VREF register.The default calibration value can be overridden by the user by writing to the CALIB bit group.

The embedded Voltage Regulator (VREG) is an internal voltage regulator that supplies the core and digital logic.

The regulator has two operating modes:

z

a normal operating mode: used when the CPU and peripherals are running

z

a low-power operating mode: used when the regulator draws small static current. By default, this mode is used in 
standby sleep mode. It is possible to have the voltage regulator operate in normal mode when the chip is in 
standby sleep mode: this is done by setting the VREG.RUNSTDBY bit.

The low-power operating mode has two possible configurations in standby sleep mode:

z

a low drive configuration, this is the default setting (the VREG.FORCELDO bit is cleared),

z

a high drive configuration: this setting is required for higher loads in standby sleep mode (case where several 
modules are up despite the standby mode). To activate this configuration, the FORCELDO bit 
(VREG.FORCELDO) in the VREG register must be set.

The internal voltage regulator system contains an internal brown-out detector(BOD12) on VDDCORE. BOD12 is 
calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration must not be 
changed to assure the correct behavior of the BOD12. The BOD12 can generate either an interrupt or a reset when 
VDDCORE crosses below the preset brown-out level. The BOD12 is always disabled in standby sleep mode.

Not applicable.

The SYSCTRL has the following interrupt sources: 

z

XOSCRDY - Multipurpose Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSCRDY bit is detected

z

XOSC32KRDY - 32kHz Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSC32KRDY bit is detected

z

OSC32KRDY - 32kHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC32KRDY bit is detected

z

OSC8MRDY - 8MHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC8MRDY bit is detected

z

DFLLRDY - DFLL48M Ready: A “0-to-1” transition on the PCLKSR.DFLLRDY bit is detected

z

DFLLOOB - DFLL48M Out Of Boundaries: A “0-to-1” transition on the PCLKSR.DFLLOOB bit is detected

z

DFLLLOCKF - DFLL48M Fine Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKF bit is detected

z

DFLLLOCKC - DFLL48M Coarse Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKC bit is detected

z

DFLLRCS - DFLL48M Reference Clock has Stopped: A “0-to-1” transition on the PCLKSR.DFLLRCS bit is detected

z

BOD33RDY - BOD33 Ready: A “0-to-1” transition on the PCLKSR.BOD33RDY bit is detected

z

BOD33DET - BOD33 Detection: A “0-to-1” transition on the PCLKSR.BOD33DET bit is detected. This is an 
asynchronous interrupt and can be used to wake-up the device from any sleep mode.

z

B33SRDY - BOD33 Synchronization Ready: A “0-to-1” transition on the PCLKSR.B33SRDY bit is detected

z

PLL Lock (LOCK): Indicates that the DPLL Lock bit is asserted.

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Δvoltage

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