Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
169
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
16.8.4 Power and Clocks Status
Name:
PCLKSR
Offset:
0x0C
Reset:
0x00000000
Property:
-
z
Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 17 – DPLLLTO: DPLL Lock Timeout
0: DPLL Lock time-out not detected.
1: DPLL Lock time-out detected.
0: DPLL Lock time-out not detected.
1: DPLL Lock time-out detected.
z
Bit 16 – DPLLLCKF: DPLL Lock Fall
0: DPLL Lock fall edge not detected.
1: DPLL Lock fall edge detected.
0: DPLL Lock fall edge not detected.
1: DPLL Lock fall edge detected.
z
Bit 15 – DPLLLCKR: DPLL Lock Rise
0: DPLL Lock rise edge not detected.
1: DPLL Lock fall edge detected.
0: DPLL Lock rise edge not detected.
1: DPLL Lock fall edge detected.
z
Bits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DPLLLTO
DPLLLCKF
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DPLLLCKR
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DFLLLCKC
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0