Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
195
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
16.8.17 DPLL Control A
Name:
DPLLCTRLA
Offset:
0x44
Reset:
0x80
Property:
Write-Protected
z
Bit 7 – ONDEMAND: On Demand Clock Activation
0: The DPLL is always on when enabled.
1: The DPLL is activated only when a peripheral request the DPLL as a source clock. The DPLLCTRLA.ENABLE
bit must be one to validate that operation, otherwise the peripheral request has no effect.
0: The DPLL is always on when enabled.
1: The DPLL is activated only when a peripheral request the DPLL as a source clock. The DPLLCTRLA.ENABLE
bit must be one to validate that operation, otherwise the peripheral request has no effect.
z
Bit 6 – RUNSTDBY: Run in Standby
0: The DPLL is disabled in standby sleep mode.
1: The DPLL is not stopped in standby sleep mode.
0: The DPLL is disabled in standby sleep mode.
1: The DPLL is not stopped in standby sleep mode.
z
Bits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – ENABLE: DPLL Enable
0: The DPLL is disabled.
1: The DPLL is enabled.
The software operation of enabling or disabling the DPLL takes a few clock cycles, so check the DPLLSTA-
TUS.ENABLE status bit to identify when the DPLL is successfully activated or disabled.
0: The DPLL is disabled.
1: The DPLL is enabled.
The software operation of enabling or disabling the DPLL takes a few clock cycles, so check the DPLLSTA-
TUS.ENABLE status bit to identify when the DPLL is successfully activated or disabled.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
ENABLE
Access
R/W
R/W
R
R
R
R
R/W
R
Reset
1
0
0
0
0
0
0
0