Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

202

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the 
following registers:

z

Interrupt Flag Status and Clear register (

)

Write-protection is denoted by the Write-Protection property in the register description. 

When the CPU is halted in debug mode, all write-protection is automatically disabled.

Write-protection does not apply for accesses through an external debugger. Refer to 

Not applicable.

The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from 
error situations such as runaway code by issuing a reset. When enabled, the WDT is a constantly running timer that is 
configured to a predefined time-out period. Before the end of the time-out period, the WDT should be reconfigured.

The WDT has two modes of operation, normal and window. Additionally, the user can enable Early Warning interrupt 
generation in each of the modes. The description for each of the basic modes is given below. The settings in the Control 
register (

) and the Interrupt Enable register (INTENCLR/SET - refer to 

operation, as illustrated in 

.

The WDT operating modes are determined by settings of Enable bit in CTRL register (CTRL.ENABLE), Window Mode 
Enable bit in CTRL register (CTRL.WEN) and Early Warning Interrupt Enable bit in INTENSET/INTENCLR registers 
(INTENSET.EW/ EW.INTENCLR.EW)

The following bits are enable-protected:

z

Window Mode Enable in the Control register (CTRL.WEN)

z

Always-On in the Control register (CTRL-ALWAYSON)

The following registers are enable-protected:

z

Configuration register (

)

z

Early Warning Interrupt Control register (

)

Any writes to these bits or registers when the WDT is enabled or is being enabled (CTRL.ENABLE is one) will be 
discarded. Writes to these registers while the WDT is being disabled will be completed after the disabling is complete. 

0

x

x

Stopped

1

0

0

Normal

1

0

1

Normal with Early Warning interrupt

1

1

0

Window

1

1

1

Window with Early Warning interrupt