Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt 
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is 
cleared, the interrupt is disabled or the WDT is reset. See 

 for details on how to clear interrupt flags. 

The WDT has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine 
which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 

Due to the asynchronicity between CLK_WDT_APB and GCLK_WDT some registers must be synchronized when 
accessed. A register can require:

z

Synchronization when written

z

Synchronization when read

z

Synchronization when written and read

z

No synchronization

When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register 
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization 
Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization 
Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).

If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All 
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is 
stalled.

The following registers need synchronization when written:

z

Control register (

z

Clear register (

)

Write-synchronization is denoted by the Write-Synchronized property in the register description.