Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
269
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
the static scheme there is a risk of high channel numbers never being granted access as the active channel. This can be
avoided using a dynamic arbitration scheme.
avoided using a dynamic arbitration scheme.
Figure 19-5. Static Priority
The dynamic arbitration scheme available in the DMAC is round-robin. Round-robin arbitration is enabled by writing
.RRLVLENx to one, for a given priority level x. With the round-robin scheme, the channel number of the last
channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel
within the same priority level, as shown in
within the same priority level, as shown in
. The channel number of the last channel being granted access as
the active channel, will be stored in the Level x Channel Priority Number bit group in the Priority Control 0
register(
register(
.LVLPRIx), for the corresponding priority level.
Figure 19-6. Round-Robin Scheduling
19.6.2.5 Data Transmission
Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding
transfer descriptor has to be initialized and the arbiter has to grant the DMA channel access as the active channel.
transfer descriptor has to be initialized and the arbiter has to grant the DMA channel access as the active channel.
Once the arbiter has granted a DMA channel access as the active channel (refer to
) the transfer descriptor
for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active
channel. Depending on if it is a new or ongoing block transfer, the transfer descriptor will either be fetched from the
descriptor memory section (
channel. Depending on if it is a new or ongoing block transfer, the transfer descriptor will either be fetched from the
descriptor memory section (
) or the write-back memory section (
the DMAC will read the data from the current source address and write it to the current destination address. For further
details on how the current source and destination addresses are calculated, refer to
details on how the current source and destination addresses are calculated, refer to
Channel 0
Channel N
Channel x
Channel x+1
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Lowest Channel
Highest Priority
Lowest Priority
Highest Channel
Channel 0
Channel N
Channel x
Channel x+1
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Lowest Priority
Highest Priority
Channel x last acknowledged request
Channel 0
Channel N
Channel x
Channel x+1
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Lowest Priority
Highest Priority
Channel x+2
Channel (x+1) last acknowledged request