Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
297
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
z
Bit 23 – RRLVLEN2: Level 2 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 2 priority.
1: Round-robin scheduling scheme for channels with level 2 priority.
For details on scheduling schemes, refer to
0: Static scheduling scheme for channels with level 2 priority.
1: Round-robin scheduling scheme for channels with level 2 priority.
For details on scheduling schemes, refer to
z
Bits 22:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 19:16 – LVLPRI2[3:0]: Level 2 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2 is one) for priority level 2, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 2.
When static arbitration is enabled (PRICTRL0.RRLVLEN2 is zero) for priority level 2, and the value of this bit
group is non-zero, it will affect the static priority scheme. If the value of this bit group is x, channel x will have the
highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum
number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from
channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN2 written to zero).
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2 is one) for priority level 2, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 2.
When static arbitration is enabled (PRICTRL0.RRLVLEN2 is zero) for priority level 2, and the value of this bit
group is non-zero, it will affect the static priority scheme. If the value of this bit group is x, channel x will have the
highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum
number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from
channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN2 written to zero).
z
Bit 15 – RRLVLEN1: Level 1 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 1 priority.
1: Round-robin scheduling scheme for channels with level 1 priority.
For details on scheduling schemes, refer to
0: Static scheduling scheme for channels with level 1 priority.
1: Round-robin scheduling scheme for channels with level 1 priority.
For details on scheduling schemes, refer to
z
Bits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – LVLPRI1[3:0]: Level 1 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1 is one) for priority level 1, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 1.
When static arbitration is enabled (PRICTRL0.RRLVLEN1 is zero) for priority level 1, and the value of this bit
group is non-zero, it will affect the static priority scheme. If the value of this bit group is x, channel x will have the
highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum
number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from
channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN1 written to zero).
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1 is one) for priority level 1, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 1.
When static arbitration is enabled (PRICTRL0.RRLVLEN1 is zero) for priority level 1, and the value of this bit
group is non-zero, it will affect the static priority scheme. If the value of this bit group is x, channel x will have the
highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum
number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease from
channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN1 written to zero).
z
Bit 7 – RRLVLEN0: Level 0 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 0 priority.
1: Round-robin scheduling scheme for channels with level 0 priority.
For details on scheduling schemes, refer to
0: Static scheduling scheme for channels with level 0 priority.
1: Round-robin scheduling scheme for channels with level 0 priority.
For details on scheduling schemes, refer to
z
Bits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:0 – LVLPRI0[3:0]: Level 0 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0 is one) for priority level 0, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 0.
When static arbitration is enabled (PRICTRL0.RRLVLEN0 is zero) for priority level 0, and the value of this bit
group is non-zero, it will affect the static priority scheme. If the value of this bit group is x, channel x will have the
highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0 is one) for priority level 0, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 0.
When static arbitration is enabled (PRICTRL0.RRLVLEN0 is zero) for priority level 0, and the value of this bit
group is non-zero, it will affect the static priority scheme. If the value of this bit group is x, channel x will have the
highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum