Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
304
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.8.1.14 Active Channel and Levels
Name:
ACTIVE
Offset:
0x30
Reset:
0x00000000
Property:
-
z
Bits 31:16 – BTCNT[15:0]: Active Channel Block Transfer Count
These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel
and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel
access. The value is valid only when the active channel active busy flag (ABUSY) is set.
These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel
and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel
access. The value is valid only when the active channel active busy flag (ABUSY) is set.
z
Bit 15 – ABUSY: Active Channel Busy
This bit is cleared when the active transfer count is written back in the Write-Back memory section.
This flag is set when the next descriptor transfer count is read from the Write-Back memory section.
This bit is cleared when the active transfer count is written back in the Write-Back memory section.
This flag is set when the next descriptor transfer count is read from the Write-Back memory section.
z
Bits 14:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 12:8 – ID[4:0]: Active Channel ID
These bits hold the channel index currently stored in the active channel registers. The value is updated each time
the arbiter grants a new channel transfer access request.
These bits hold the channel index currently stored in the active channel registers. The value is updated each time
the arbiter grants a new channel transfer access request.
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
Bit
31
30
29
28
27
26
25
24
BTCNT[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
BTCNT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
ABUSY
ID[4:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
LVLEX3
LVLEX2
LVLEX1
LVLEX0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0