Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
445
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
25.8.1 Control A
Name:
CTRLA
Offset:
0x00
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected, Write-Synchronized
z
Bit 31 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 30 – DORD: Data Order
This bit indicates the data order when a character is shifted out from the Data register.
0: MSB is transmitted first.
1: LSB is transmitted first.
This bit is not synchronized.
This bit indicates the data order when a character is shifted out from the Data register.
0: MSB is transmitted first.
1: LSB is transmitted first.
This bit is not synchronized.
z
Bit 29 – CPOL: Clock Polarity
This bit indicates the relationship between data output change and data input sampling in synchronous mode.
This bit is not synchronized.
This bit indicates the relationship between data output change and data input sampling in synchronous mode.
This bit is not synchronized.
Bit
31
30
29
28
27
26
25
24
DORD
CPOL
CMODE
FORM[3:0]
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
SAMPA[1:0]
RXPO[1:0]
TXPO[1:0]
Access
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
SAMPR[2:0]
IBON
Access
R/W
R/W
R/W
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
MODE[2:0]
ENABLE
SWRST
Access
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0