Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
467
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
for details on the pin mapping for this peripheral. One signal
can be mapped to one of several pins.
26.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
26.5.1 I/O Lines
Using the SERCOM’s I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to
When the SERCOM is configured for SPI operation, the pins should be configured according to
. If the
receiver is disabled, the data input pin can be used for other purposes. In master mode the slave select line (_SS) is
hardware controlled when Master Slave Select Enable (CTRLB.MSSEN) is set to one.
hardware controlled when Master Slave Select Enable (CTRLB.MSSEN) is set to one.
Table 26-1. SPI Pin Configuration
The combined configuration of PORT and the Data In/Data Out and Data Out Pinout bit groups in Control A register will
define the physical position of the SPI signals in
define the physical position of the SPI signals in
26.5.2 Power Management
The SPI can continue to operate in any sleep mode. The SPI interrupts can be used to wake up the device from sleep
modes. Refer to
modes. Refer to
for details on the different sleep modes.
26.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_SERCOMx_APB can be found in the Peripheral Clock Masking section in the
state of CLK_SERCOMx_APB can be found in the Peripheral Clock Masking section in the
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in
the Generic Clock Controller before using the SPI. Refer to
the Generic Clock Controller before using the SPI. Refer to
for details.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to
registers will require synchronization between the clock domains. Refer to
details.
26.5.4 DMA
The DMA request lines are connected to the DMA controller (DMAC). Using the SERCOM DMA requests, requires
the DMA controller to be configured first. Refer to
the DMA controller to be configured first. Refer to
details
.
26.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SPI, interrupts requires the Interrupt
Controller to be configured first. Refer to
Controller to be configured first. Refer to
for details.
Pin
Master SPI
Slave SPI
MOSI
Output
Input
MISO
Input
Output
SCK
Output
Input
_SS
Output (CTRLB.MSSEN=1)
Input