Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

The I

2

C master starts a bus transaction by writing ADDR.ADDR with the I

2

C slave address and the direction bit. If the bus 

is busy, the I

2

C master will wait until the bus becomes idle before continuing the operation. When the bus is idle, the I

2

C 

master will issue a start condition on the bus. The I

2

C master will then transmit an address packet using the address 

written to ADDR.ADDR.

After the address packet has been transmitted by the I

2

C master, one of four cases will arise, based on arbitration and 

transfer direction.

If arbitration was lost during transmission of the address packet, the Master on Bus bit in the Interrupt Flag register 
(INTFLAG.MB) and the Arbitration Lost bit in the Status register (STATUS.ARBLOST) are both set. Serial data output to 
SDA is disabled, and the SCL is released, which disables clock stretching. In effect the I

2

C master is no longer allowed to 

perform any operation on the bus until the bus is idle again. A bus error will behave similarly to the arbitration lost 
condition. In this case, the MB interrupt flag and Master Bus Error bit in the Status register (STATUS.BUSERR) are both 
set in addition to STATUS.ARBLOST. 

The Master Received Not Acknowledge bit in the Status register (STATUS.RXNACK) will always contain the last 
successfully received acknowledge or not acknowledge indication.

In this case, software will typically inform the application code of the condition and then clear the interrupt flag before 
exiting the interrupt routine. No other flags have to be cleared at this point, because all flags will be cleared automatically 
the next time the ADDR.ADDR register is written. 

If no I

2

C slave device responds to the address packet, then the INTFLAG.MB interrupt flag is set and STATUS.RXNACK 

is set. The clock hold is active at this point, preventing further activity on the bus.

The missing ACK response can indicate that the I

2

C slave is busy with other tasks or sleeping and, therefore, not able to 

respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the address 

Software interaction

The master provides data 
on the bus

Addressed slave provides 
data on the bus