Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
529
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
All interrupt flags (INTFLAG.DRDY, INTFLAG.AMATCH and INTFLAG.PREC) are automatically cleared when a
command is given.
This bit is not enable-protected.
command is given.
This bit is not enable-protected.
Table 27-7. Command Description
z
Bits 15:14 – AMODE[1:0]: Address Mode
These bits set the addressing mode according to
These bits set the addressing mode according to
.
Table 27-8. Address Mode Description
Note:
1. See
for additional information.
These bits are not write-synchronized.
z
Bits 13:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 10– AACKEN: Automatic Acknowledge Enable
This bit enables the address to be automatically acknowledged if there is an address match.
0: Automatic acknowledge is disabled.
1: Automatic acknowledge is enabled.
This bit is not write-synchronized.
This bit enables the address to be automatically acknowledged if there is an address match.
0: Automatic acknowledge is disabled.
1: Automatic acknowledge is enabled.
This bit is not write-synchronized.
CMD[1:0]
DIR
Action
0x0
X
(No action)
0x1
X
(Reserved)
0x2
Used to complete a transaction in response to a data interrupt (DRDY)
0 (Master write)
Execute acknowledge action succeeded by waiting for any start (S/Sr) condition
1 (Master read)
Wait for any start (S/Sr) condition
0x3
Used in response to an address interrupt (AMATCH)
0 (Master write)
Execute acknowledge action succeeded by reception of next byte
1 (Master read)
Execute acknowledge action succeeded by slave data interrupt
Used in response to a data interrupt (DRDY)
0 (Master write)
Execute acknowledge action succeeded by reception of next byte
1 (Master read)
Execute a byte read operation followed by ACK/NACK reception
Value
Name
Description
0x0
MASK
The slave responds to the address written in ADDR.ADDR masked by the value in
ADDR.ADDRMASK
ADDR.ADDRMASK
(1)
.
0x1
2_ADDRS
The slave responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK.
0x2
RANGE
The slave responds to the range of addresses between and including ADDR.ADDR and
ADDR.ADDRMASK. ADDR.ADDR is the upper limit.
ADDR.ADDRMASK. ADDR.ADDR is the upper limit.
0x3
-
Reserved.