Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
534
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
27.8.1.6 Status
Name:
STATUS
Offset:
0x1A
Reset:
0x0000
Property:
-
z
Bits 15:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 10 – HS: High-speed
This bit is set if the slave detects a START followed by a Master Code transmission.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status. However, this flag is automatically cleared when a STOP is received.
This bit is set if the slave detects a START followed by a Master Code transmission.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status. However, this flag is automatically cleared when a STOP is received.
z
Bit 9 – SEXTTOUT: Slave SCL Low Extend Time-Out
This bit is set if a slave SCL low extend time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD)
or when INTFLAG.AMATCH is cleared.
0: No SCL low extend time-out has occurred.
1: SCL low extend time-out has occurred.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status.
This bit is set if a slave SCL low extend time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD)
or when INTFLAG.AMATCH is cleared.
0: No SCL low extend time-out has occurred.
1: SCL low extend time-out has occurred.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the status.
z
Bit 8 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 7 – CLKHOLD: Clock Hold
The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low, stretching the I
The slave Clock Hold bit (STATUS.CLKHOLD) is set when the slave is holding the SCL line low, stretching the I
2
C
clock. Software should consider this bit a read-only status flag that is set when INTFLAG.DRDY or INT-
FLAG.AMATCH is set.
This bit is automatically cleared when the corresponding interrupt is also cleared.
FLAG.AMATCH is set.
This bit is automatically cleared when the corresponding interrupt is also cleared.
z
Bit 6 – LOWTOUT: SCL Low Time-out
This bit is set if an SCL low time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD)
or when INTFLAG.AMATCH is cleared.
This bit is set if an SCL low time-out occurs.
This bit is cleared automatically if responding to a new start condition with ACK or NACK (write 3 to CTRLB.CMD)
or when INTFLAG.AMATCH is cleared.
Bit
15
14
13
12
11
10
9
8
HS
SEXTTOUT
Access
R
R
R
R
R
R/W
R/W
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CLKHOLD
LOWTOUT
SR
DIR
RXNACK
COLL
BUSERR
Access
R
R/W
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0