Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
539
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
27.8.1.9 Data
Name:
DATA
Offset:
0x28
Reset:
0x0000
Property:
Write-Synchronized, Read-Synchronized
z
Bits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:0 – DATA[7:0]: Data
The slave data register I/O location (DATA.DATA) provides access to the master transmit and receive data buf-
fers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by
the slave (STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition
has been received.
Accessing DATA.DATA auto-triggers I
The slave data register I/O location (DATA.DATA) provides access to the master transmit and receive data buf-
fers. Reading valid data or writing data to be transmitted can be successfully done only when SCL is held low by
the slave (STATUS.CLKHOLD is set). An exception occurs when reading the last data byte after the stop condition
has been received.
Accessing DATA.DATA auto-triggers I
2
C bus operations. The operation performed depends on the state of
CTRLB.ACKACT, CTRLB.SMEN and the type of access (read/write).
Writing or reading DATA.DATA when not in smart mode does not require synchronization.
Writing or reading DATA.DATA when not in smart mode does not require synchronization.
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0