Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
550
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
27.8.2.6 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x18
Reset:
0x00
Property:
-
z
Bit 7– ERROR: Error
This flag is cleared by writing a one to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STA-
TUS register. Errors that will set this flag are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and
BUSERR.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
This flag is cleared by writing a one to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the STA-
TUS register. Errors that will set this flag are LENERR, SEXTTOUT, MEXTTOUT, LOWTOUT, ARBLOST, and
BUSERR.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
z
Bits 6:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – SB: Slave on Bus
The Slave on Bus flag (SB) is set when a byte is successfully received in master read mode, i.e., no arbitration lost
or bus error occurred during the operation. When this flag is set, the master forces the SCL line low, stretching the
I
The Slave on Bus flag (SB) is set when a byte is successfully received in master read mode, i.e., no arbitration lost
or bus error occurred during the operation. When this flag is set, the master forces the SCL line low, stretching the
I
2
C clock period. The SCL line will be released and SB will be cleared on one of the following actions:
z
Writing to ADDR.ADDR
z
Writing to DATA.DATA
z
Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
z
Writing a valid command to CTRLB.CMD
Writing a one to this bit location will clear the SB flag. The transaction will not continue or be terminated until one of
the above actions is performed.
Writing a zero to this bit has no effect.
the above actions is performed.
Writing a zero to this bit has no effect.
z
Bit 0 – MB: Master on Bus
The Master on Bus flag (MB) is set when a byte is transmitted in master write mode. The flag is set regardless of
the occurrence of a bus error or an arbitration lost condition. MB is also set when arbitration is lost during sending
of NACK in master read mode, and when issuing a start condition if the bus state is unknown. When this flag is set
and arbitration is not lost, the master forces the SCL line low, stretching the I
The Master on Bus flag (MB) is set when a byte is transmitted in master write mode. The flag is set regardless of
the occurrence of a bus error or an arbitration lost condition. MB is also set when arbitration is lost during sending
of NACK in master read mode, and when issuing a start condition if the bus state is unknown. When this flag is set
and arbitration is not lost, the master forces the SCL line low, stretching the I
2
C clock period. The SCL line will be
released and MB will be cleared on one of the following actions:
z
Writing to ADDR.ADDR
z
Writing to DATA.DATA
z
Reading DATA.DATA when smart mode is enabled (CTRLB.SMEN)
z
Writing a valid command to CTRLB.CMD
If arbitration is lost, writing a one to this bit location will clear the MB flag.
If arbitration is not lost, writing a one to this bit location will clear the MB flag. The transaction will not continue or be
terminated until one of the above actions is performed.
If arbitration is not lost, writing a one to this bit location will clear the MB flag. The transaction will not continue or be
terminated until one of the above actions is performed.
Bit
7
6
5
4
3
2
1
0
ERROR
SB
MB
Access
R/W
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0