Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

 in the 

 for details on the pin mapping for this 

peripheral. One signal can be mapped on several pins. 

In order to use this module, other parts of the system must be configured correctly, as described below.

Using I

2

The I

2

S pins may be multiplexed with I/O Controller lines. The user must first program the I/O Controller to assign the 

desired I

2

S pins to their peripheral function. If the I

2

S I/O lines are not used by the application, they can be used for other 

purposes by the I/O Controller. It is required to enable only the I

2

S inputs and outputs actually in use.

The I

2

S will continue to operate in any sleep mode where the selected source clocks are running.

The clock for the I

2

S bus interface (CLK_I2S_APB) is generated by the Power Manager. This clock is disabled at reset, 

and can be enabled in the Power Manager. It is recommended to disable the I

2

S before disabling the clock, to avoid 

freezing the I

2

S in an undefined state.

There are two generic clocks, GCLK_I2S_0 and GCLK_I2S_1 connected the I

2

S peripheral, one for each I

2

S clock unit. 

The generic clocks (GCLK_I2S_n, n=0..1) can be set to a wide range of frequencies and clock sources. The 
GCLK_I2S_n must be enabled and configured before use. Refer to the 

 

section for details on the generic clocks used for the I

2

S.

The generic clocks are only used in Master mode and Controller mode. In Master mode, the clock from a single clock unit 
can be used for both Serializers to handle synchronous transfers, or a separate clock from different clock units can be 
used for each Serializer to handle transfers on non-related clocks.

The DMA request lines are connected to the DMA Controller (DMAC). Using the I

2

S DMA requests requires the DMA 

Controller to be configured first. Refer to 

 for details.

The interrupt request line is connected to the interrupt controller. Using the I

2

S interrupts requires the interrupt controller 

 for details.

Not applicable.

MCKn

Master Clock for Clock Unit n

Output

SCKn

Serial Clock for Clock Unit n

Output

FSn

I

2

S Word Select or TDM Frame Sync

Output

SDm

Not Applicable

Not Applicable