Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
568
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
In Master mode, one of the generic clocks for the I
2
S must also be configured to operate at the required frequency, as
described in
z
fs is the sampling frequency that defines the frame period, e.g. 48kHz
z
CLKCTRLn.NBSLOTS defines the number of slots in each frame, e.g. 6-slot frame if NBSLOTS=5
z
CLKCTRLn.SLOTSIZE defines the number of bits in each slot, e.g. 32-bit slot if SLOTSIZE=3
z
SCKn frequency must then be (fs * number_of_slots * number_of_bits_per_slot), e.g. 9.216MHz
As an example, if a 384fs MCKn Master Clock is required, i.e. 18.432MHz (fs = 48kHz), then the I
2
S generic clock could
be at 18.432MHz and CLKCTRLn.MCKOUTDIV=0, to obtain MCKn frequency as 18.432MHz. Dividing the I
2
S generic
clock by 2, by setting CLKCTRLn.MCKDIV=1, will output the desired SCKn frequency, 9.216MHz to the SCKn pin. If
MCKn is not required, the generic clock could be set to 9.216MHz and CLKCTRLn.MCKDIV=0.
MCKn is not required, the generic clock could be set to 9.216MHz and CLKCTRLn.MCKDIV=0.
Let us consider if a 384fs MCKn Master Clock is also required, i.e. 18.432MHz, then the generic clock could be at
18.432MHz and MCLKn divided by 2, by setting CLKCTRLn.MCKDIV=1, to obtain SCKn desired frequency. If MCKn is
not required, the generic clock could be at 9.216MHz and CLKCTRLn.MCKDIV=0.
18.432MHz and MCLKn divided by 2, by setting CLKCTRLn.MCKDIV=1, to obtain SCKn desired frequency. If MCKn is
not required, the generic clock could be at 9.216MHz and CLKCTRLn.MCKDIV=0.
Once the configuration has been written, the I
2
S Clock Units and Serializers can be enabled by writing a one to the
CKENn and SERENm bits and to the ENABLE bit in the Control register (CTRLA). The Clock Unit n can be enabled
alone, in Controller Mode, to output clocks to the MCKn, SCKn, and FSn pins. The Clock Units must be enabled if
Serializers are enabled.
alone, in Controller Mode, to output clocks to the MCKn, SCKn, and FSn pins. The Clock Units must be enabled if
Serializers are enabled.
The Clock Units and Serializers can be disabled independently by writing a zero to CTRLA.CKENn, or CTRLA.SERENm
respectively. Once requested to stop, they will only stop when the pending transmit frames will be completed, if any.
When requested to stop, the ongoing reception of the current slot will be completed and then the Serializer will be
stopped.
respectively. Once requested to stop, they will only stop when the pending transmit frames will be completed, if any.
When requested to stop, the ongoing reception of the current slot will be completed and then the Serializer will be
stopped.
28.6.2 Basic Operation
The Receiver can be operated by reading the Data Holding register (DATAm), whenever the Receive Ready m bit in the
Interrupt Flag Status and Clear register (INTFLAG.RXRDYm) is set. Successive values read from DATAm register will
correspond to the samples from the left and right audio channels. In TDM mode, the successive values read from
DATAm register correspond to the first slot to the last slot. For instance, if I
Interrupt Flag Status and Clear register (INTFLAG.RXRDYm) is set. Successive values read from DATAm register will
correspond to the samples from the left and right audio channels. In TDM mode, the successive values read from
DATAm register correspond to the first slot to the last slot. For instance, if I
2
S is configured in TDM mode with 4 slots in a
frame, then successive values written to DATAm register correspond to first, second, third, and fourth slot. The number
of slots in TDM is configured in CLKCTRLn.NBSLOTS.
of slots in TDM is configured in CLKCTRLn.NBSLOTS.
The Transmitter can be operated by writing to the Data Holding register (DATAm), whenever the Transmit Ready m bit in
the Interrupt Flag Status and Clear register (INTFLAG.TXRDYm) is set. Successive values written to DATAm register
should correspond to the samples from the left and right audio channels. In TDM mode, the successive values written to
DATAm register correspond to the first, second, third, slot to the last slot. The number of slots in TDM is configured in
CLKCTRLn.NBSLOTS.
the Interrupt Flag Status and Clear register (INTFLAG.TXRDYm) is set. Successive values written to DATAm register
should correspond to the samples from the left and right audio channels. In TDM mode, the successive values written to
DATAm register correspond to the first, second, third, slot to the last slot. The number of slots in TDM is configured in
CLKCTRLn.NBSLOTS.
The Receive Ready and Transmit Ready bits can be polled by reading the INTFLAG register.
The processor load can be reduced by enabling interrupt-driven operation. The RXRDYm and/or TXRDYm interrupt
requests can be enabled by writing a one to the corresponding bit in the Interrupt Enable register (INTENSET). The
interrupt service routine associated to the I
requests can be enabled by writing a one to the corresponding bit in the Interrupt Enable register (INTENSET). The
interrupt service routine associated to the I
2
S interrupt request will then be executed whenever Receive Ready or
Transmit Ready status bits are set.
The processor load can be further reduced by enabling DMA-driven operation. The DMAC channels support up to four
trigger source from I
trigger source from I
2
S peripheral. These four trigger sources in DMAC channel are I2S RX 0, I2S RX 1, I2S TX 0 and
I2S TX 1. For further reference in this chapter, these can be called as, I2S_DMAC_ID_RX_m and I2S_DMAC_ID_TX_m
triggers (m=0..1). By using these trigger sources, one DMA data transfer will be executed whenever Receive Ready or
Transmit Ready status bits are set.
triggers (m=0..1). By using these trigger sources, one DMA data transfer will be executed whenever Receive Ready or
Transmit Ready status bits are set.
28.6.2.1 Master Clock, Serial Clock, and Frame Sync Generation
The generation of clocks in the I
2
S is described in