Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
571
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Figure 28-4. I
2
S Clocks Generation
28.6.2.2 Data Holding Registers
The I
2
S user interface includes a Data m register (DATAm) for each Serializer m. They are used to access data samples
for all data slots.
Data Reception Mode
In Receiver mode, when a new data word is available in the DATAm register, Receive Ready bit (RXRDYm) in the
Interrupt Flag Status and Clear register (INTFLAG) is set. Reading the DATAm register will clear this bit.
Interrupt Flag Status and Clear register (INTFLAG) is set. Reading the DATAm register will clear this bit.
A receive overrun condition occurs if a new data word becomes available before the previous data word has been read
from the DATAm register. Then, Receive Overrun (RXORm) bit in INTFLAG will be set. This interrupt can be cleared by
writing a one to INTFLAG.RXORm bit.
from the DATAm register. Then, Receive Overrun (RXORm) bit in INTFLAG will be set. This interrupt can be cleared by
writing a one to INTFLAG.RXORm bit.
MCKEN
MCKSEL
MCKDIV
SCKSEL
SCKSEL
SLOTSIZE
FSSEL
FSINV
FSSEL
NBSLOTS
1
0
MCKOUTINV
1 0
1 0
0 1
1 0
1 0
1 0
SCKOUTINV
1 0
FSOUTINV
MCKOUTDIV
MCKn
SCKn
FSn
GCLK_I2S_n
clk_mck_div
clk_sck[n]
slot_nb
fs_mast
frame_sync
DIV
DIV
DIV
DIV