Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
584
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
1: The Master Clock n division and output is enabled.
z
Bit 17 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 16 – MCKSEL: Master Clock Select
This field selects the source of the Master Clock n. Refer to
This field selects the source of the Master Clock n. Refer to
for details.
Table 28-6. Master Clock Select
z
Bits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 12 – SCKSEL: Serial Clock Select
This field selects the source of the Serial Clock n. Refer to
This field selects the source of the Serial Clock n. Refer to
Table 28-7. Serial Clock Select
z
Bit 11 – FSINV: Frame Sync Invert
0: The Frame Sync n is used without inversion.
1: The Frame Sync n is inverted before being used.
0: The Frame Sync n is used without inversion.
1: The Frame Sync n is inverted before being used.
z
Bits 10:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 8 – FSSEL: Frame Sync Select
This field selects the source of the Frame Sync n. Refer to
This field selects the source of the Frame Sync n. Refer to
Table 28-8. Frame Sync Select
MCKSEL
Name
Description
0x0
GCLK
GCLK_I2S_n is used as Master Clock n source
0x1
MCKPIN
MCKn input pin is used as Master Clock n source
SCKSEL
Name
Description
0x0
MCKDIV
Divided Master Clock n is used as Serial Clock n source
0x1
SCKPIN
SCKn input pin is used as Serial Clock n source
FSSEL
Name
Description
0x0
SCKDIV
Divided Serial Clock n is used as Frame Sync n source
0x1
FSPIN
FSn input pin is used as Frame Sync n source