Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
588
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
28.9.4 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name:
INTENSET
Offset:
0x10
Reset:
0x0000
Property:
Write-Protected
z
Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 13:12 – TXURx [x=1..0]: Transmit Underrun x Interrupt Enable
0: The Transmit Underrun interrupt is disabled.
1: The Transmit Underrun interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Transmit Underrun Interrupt Enable bit, which enables the Transmit Underrun
interrupt.
0: The Transmit Underrun interrupt is disabled.
1: The Transmit Underrun interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Transmit Underrun Interrupt Enable bit, which enables the Transmit Underrun
interrupt.
z
Bits 11:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 9:8 – TXRDYx [x=1..0]: Transmit Ready x Interrupt Enable
0: The Transmit Ready interrupt is disabled.
1: The Transmit Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Transmit Ready Interrupt Enable bit, which enables the Transmit Ready
interrupt.
0: The Transmit Ready interrupt is disabled.
1: The Transmit Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Transmit Ready Interrupt Enable bit, which enables the Transmit Ready
interrupt.
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:4 – RXORx [x=1..0]: Receive Overrun x Interrupt Enable
0: The Receive Overrun interrupt is disabled.
1: The Receive Overrun interrupt is enabled.
Writing a zero to this bit has no effect.
0: The Receive Overrun interrupt is disabled.
1: The Receive Overrun interrupt is enabled.
Writing a zero to this bit has no effect.
Bit
15
14
13
12
11
10
9
8
TXUR1
TXUR0
TXRDY1
TXRDY0
Access
R
R
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RXOR1
RXOR0
RXRDY1
RXRDY0
Access
R
R
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0