Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

z

No synchronization

When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register 
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization 
Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization 
Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).

If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All 
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is 
stalled.

The following bits need synchronization when written:

z

Software Reset bit in the Control A register (CTRLA.SWRST)

z

Enable bit in the Control A register (CTRLA.ENABLE)

Write-synchronization is denoted by the Write-Synchronized property in the register description.

The following registers need synchronization when written:

z

Control B Clear register (CTRLBCLR)

z

Control B Set register (CTRLBSET)

z

Control C register (CTRLC)

z

Count Value register (COUNT)

z

Period Value register (PERIOD)

z

Compare/Capture Value registers (CCx)

Write-synchronization is denoted by the Write-Synchronized property in the register description.

The following registers need synchronization when read:

z

Control B Clear register (CTRLBCLR)

z

Control B Set register (CTRLBSET)

z

Control C register (CTRLC)

z

Count Value register (COUNT)

z

Period Value register (PERIOD)

z

Compare/Capture Value registers (CCx)

Read-synchronization is denoted by the Read-Synchronized property in the register description.