Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
624
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
29.8.5 Control C
Name:
CTRLC
Offset:
0x06
Reset:
0x00
Property:
Write-Protected, Write-Synchronized, Read-Synchronized
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:4 – CPTENx: Capture Channel x Enable
These bits are used to select whether channel x is a capture or a compare channel.
Writing a one to CPTENx enables capture on channel x.
Writing a zero to CPTENx disables capture on channel x.
These bits are used to select whether channel x is a capture or a compare channel.
Writing a one to CPTENx enables capture on channel x.
Writing a zero to CPTENx disables capture on channel x.
z
Bits 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 1:0 – INVENx: Waveform Output x Invert Enable
These bits are used to select inversion on the output of channel x.
Writing a one to INVENx inverts the output from WO[x].
Writing a zero to INVENx disables inversion of the output from WO[x].
These bits are used to select inversion on the output of channel x.
Writing a one to INVENx inverts the output from WO[x].
Writing a zero to INVENx disables inversion of the output from WO[x].
Bit
7
6
5
4
3
2
1
0
CPTEN1
CPTEN0
INVEN1
INVEN0
Access
R
R
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0