Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each TCC clock 
cycle (CLK_TCC_CNT). A counter clear or reload mark the end of current counter cycle and the start of a new one.

The counter will count in the direction set by the direction (CTRLBSET.DIR or CTRLBCLR.DIR) bit for each clock until it 
reaches TOP or ZERO. A clear operation occurs when the TOP is reached while up-counting, the counter will be set to 
ZERO (cleared) on the next clock cycle. A reload operation occurs when the ZERO is reached while down-counting, the 
counter is reloaded with the period register (PER) value.

The counter value is continuously compared with the period (PER) and ZERO value to determine if the counter has 
reached TOP or ZERO. Based on this comparison, the Overflow Interrupt Flag in the Interrupt Flag Status and Clear 
register (INTFLAG.OVF)is set whenever the counter value matches with TOP / ZERO. This can be used to trigger an 
interrupt, a DMA request, or an event. If the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is set, the 
compare match (with TOP/ZERO) will stop the counting operation.

Up-counting is enabled by writing a one to the Direction bit in the Control B Clear register (CTRLBCLR.DIR). Down-
counting is enabled by writing a one to the Direction bit in the Control B Set register (CTRLBSET.DIR).

As shown in 

, it is possible to change the counter value (by writing directly in the Count register) even when 

the counter is running. The write access has higher priority than count, clear, or reload. The direction of the counter can 
also be changed during normal operation. Due to asynchronous clock domains, the internal counter settings are written 
when the synchronization is complete. 

Normal operation must be used when using the counter as timer base for the capture channels.

A stop command can be issued from software by using TCC Command bits in Control B Set register (CTRLBSET.CMD = 
STOP) or when the stop event action is configured in the Input Event1 Action bits in Event Control register 
(EVCTRL.EVACT1 = STOP).

When a stop is detected while the counter is running, the counter will maintain its current value. If waveform generation 
(WG) is used, all waveforms are set to a state defined in Non-Recoverable State x Output Enable bit and Non-

TCCx EV0/1

COUNT

PRESCALER

PRESCALER

EVACT 0/1

GCLK_TCC

GCLK_TCC / 

{1,2,4,8,64,256,1024 }

CLK_TCC_COUNT