Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
706
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Writing a one to this bit clears the Non-Recoverable Fault 0 interrupt flag.
z
Bit 13 – FAULTB: Recoverable Fault B
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Recoverable Fault B interrupt flag.
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Recoverable Fault B interrupt flag.
z
Bit 12 – FAULTA: Recoverable Fault A
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault A occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Recoverable Fault A interrupt flag.
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault A occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Recoverable Fault A interrupt flag.
z
Bit 11 – DFS: Non-Recoverable Debug Fault
This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Debug Fault State interrupt flag.
This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Debug Fault State interrupt flag.
z
Bits 10:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3 – ERR: Error
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one. In which case there is nowhere to store the new capture.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Error interrupt flag.
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one. In which case there is nowhere to store the new capture.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Error interrupt flag.
z
Bit 2 – CNT: Counter
This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the CNT interrupt flag.
This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the CNT interrupt flag.
z
Bit 1 – TRG: Retrigger
This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Retrigger interrupt flag.
This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Retrigger interrupt flag.
z
Bit 0 – OVF: Overflow
This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.