Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

Product codes
ATSAMD21-XPRO
Page of 1018
783
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.3.4  EndPoint Status n
Name:
EPSTATUS
Offset:
0x106 + (n x 0x20)
Reset:
0x00
Property:
Write-Protected
z
Bit 7 – BK1RDY: Bank 1 is ready
0: The bank number 1 is not ready : For IN direction Endpoints, the bank is not yet filled in. 
For Control/OUT direction Endpoints, the bank is empty.
1: The bank number 1 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction End-
points, the bank is full.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit. 
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit. 
z
Bit 6 – BK0RDY: Bank 0 is ready
0: The bank number 0 is not ready : For IN direction Endpoints, the bank is not yet filled in. For Control/OUT direc-
tion Endpoints, the bank is empty.
1: The bank number 0 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction End-
points, the bank is full.
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit. 
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit. 
z
Bit 5 – STALLRQ1: STALL bank 1 request
0: Disable STALLRQ1 feature.
1: Enable STALLRQ1 feature: a STALL handshake will be sent to the host in regards to bank1.
Writing a zero to the bit EPSTATUSCLR.STALLRQ1 will clear this bit.
Writing a one to the bit EPSTATUSSET.STALLRQ1 will set this bit. 
This bit is cleared by hardware when receiving a SETUP packet.
z
Bit 4 – STALLRQ0: STALL bank 0 request
0: Disable STALLRQ0 feature.
1: Enable STALLRQ0 feature: a STALL handshake will be sent to the host in regards to bank0.
Writing a zero to the bit EPSTATUSCLR.STALLRQ0 will clear this bit.
Writing a one to the bit EPSTATUSSET.STALLRQ0 will set this bit. 
This bit is cleared by hardware when receiving a SETUP packet.
z
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero 
when this register is written. This bit will always return zero when read.
z
Bit 2 – CURBK: Current Bank
0: The bank0 is the bank that will be used in the next single/multi USB packet.
1: The bank1 is the bank that will be used in the next single/multi USB packet.
Writing a zero to the bit EPSTATUSCLR.CURBK will clear this bit.
Bit
7
6
5
4
3
2
1
0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
CURBK
DTGLIN
DTGLOUT
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0