Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
788
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
The user should look into the descriptor table status located in ram to be informed about the error condition :
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail 1 Interrupt Enable bit and disable the corresponding interrupt
request.
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail 1 Interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 2 – TRFAIL0: Transfer Fail 0 Interrupt Enable
0: The Transfer Fail bank 0 interrupt is disabled.
1: The Transfer Fail bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 0
Interrupt Flag is set.
The user should look into the descriptor table status located in ram to be informed about the error condition :
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail 0 Interrupt Enable bit and disable the corresponding interrupt
request.
0: The Transfer Fail bank 0 interrupt is disabled.
1: The Transfer Fail bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer Fail 0
Interrupt Flag is set.
The user should look into the descriptor table status located in ram to be informed about the error condition :
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail 0 Interrupt Enable bit and disable the corresponding interrupt
request.
z
Bit 1 – TRCPT1: Transfer Complete 1 Interrupt Enable
0: The Transfer Complete 1 interrupt is disabled.
1: The Transfer Complete 1 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete 1 Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete 1 Interrupt Enable bit and disable the corresponding inter-
rupt request.
0: The Transfer Complete 1 interrupt is disabled.
1: The Transfer Complete 1 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete 1 Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete 1 Interrupt Enable bit and disable the corresponding inter-
rupt request.
z
Bit 0 – TRCPT0: Transfer Complete 0 interrupt Enable
0: The Transfer Complete bank 0 interrupt is disabled.
1: The Transfer Complete bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete 0 Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete 0 interrupt Enable bit and disable the corresponding inter-
rupt request.
0: The Transfer Complete bank 0 interrupt is disabled.
1: The Transfer Complete bank 0 interrupt is enabled and an interrupt request will be generated when the Transfer
Complete 0 Interrupt Flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete 0 interrupt Enable bit and disable the corresponding inter-
rupt request.