Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
815
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
31.8.6.5 Pipe Status Register n
Name:
PSTATUS
Offset:
0x106 + (n x 0x20)
Reset:
0x0000
Property:
Write-Protected
z
Bit 7– BK1RDY: Bank 1 is ready
0: The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not yet fill in.
1: The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
This bank is not used for Control pipe.
0: The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not yet fill in.
1: The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
This bank is not used for Control pipe.
z
Bit 6 – BK0RDY: Bank 0 is ready
0: The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is not yet fill in.
1: The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
This bank is the only one used for Control pipe.
0: The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is not yet fill in.
1: The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
This bank is the only one used for Control pipe.
z
Bit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 4 – PFREEZE: Pipe Freeze
0: The Pipe operates in normal operation.
1: The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit.
Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit.
0: The Pipe operates in normal operation.
1: The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit.
Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit.
z
This bit is also set by the hardware:
z
When a STALL handshake has been received.
z
After a PIPE has been enabled (rising of bit PEN.N).
z
When an LPM transaction has completed whatever handshake is returned or the transaction was timed-out.
z
When a pipe transfer was completed with a pipe error. See
.
When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be properly com-
pleted. PFREEZE bit will be read as “1” only when the ongoing transaction will have been completed.
pleted. PFREEZE bit will be read as “1” only when the ongoing transaction will have been completed.
z
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 2 – CURBK: Current Bank
0: The bank0 is the bank that will be used in the next single/multi USB packet.
1: The bank1 is the bank that will be used in the next single/multi USB packet.
0: The bank0 is the bank that will be used in the next single/multi USB packet.
1: The bank1 is the bank that will be used in the next single/multi USB packet.
Bit
7
6
5
4
3
2
1
0
BK1RDY
BK0RDY
PFREEZE
CURBK
DTGL
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0