Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
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Product codes
ATSAMD21-XPRO
865
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
32.8.14 Result
Name:
RESULT
Offset:
0x1A
Reset:
0x0000
Property:
Read-Synchronized
z
Bits 15:0 – RESULT[15:0]: Result Conversion Value
These bits will hold up to a 16-bit ADC result, depending on the configuration.
In single-ended without averaging mode, the ADC conversion will produce a 12-bit result, which can be left- or
right-shifted, depending on the setting of CTRLB.LEFTADJ.
If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8], while the
remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit result is required;
i.e., one can read only the high byte of the entire 16-bit register.
If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be available in bit
locations [11:0], and the result is then 12 bits long.
If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the Average
Control register (
These bits will hold up to a 16-bit ADC result, depending on the configuration.
In single-ended without averaging mode, the ADC conversion will produce a 12-bit result, which can be left- or
right-shifted, depending on the setting of CTRLB.LEFTADJ.
If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8], while the
remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit result is required;
i.e., one can read only the high byte of the entire 16-bit register.
If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be available in bit
locations [11:0], and the result is then 12 bits long.
If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the Average
Control register (
).
Bit
15
14
13
12
11
10
9
8
RESULT[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RESULT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0