Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
44
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
12.5.8 Analog Connections
Not applicable.
12.6 Debug Operation
12.6.1 Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor
debug resources:
debug resources:
z
CPU reset extension
z
Debugger probe detection
For more details on the ARM debug components, refer to the ARM Debug Interface v5Architecture Specification.
12.6.2 CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released. This
ensures that the CPU is not executing code at startup while a debugger connects to the system. It is detected on a
RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a
debugger if SWCLK is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension
bit (CRSTEXT) of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a one to
STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to zero. Writing a zero to STATUSA.CRSTEXT has no
effect. For security reasons, it is not possible to release the CPU reset extension when the device is protected by the
NVMCTRL security bit (refer to
ensures that the CPU is not executing code at startup while a debugger connects to the system. It is detected on a
RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a
debugger if SWCLK is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension
bit (CRSTEXT) of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a one to
STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to zero. Writing a zero to STATUSA.CRSTEXT has no
effect. For security reasons, it is not possible to release the CPU reset extension when the device is protected by the
NVMCTRL security bit (refer to
). Trying to do so sets the Protection Error bit (PERR) of the
Status A register (STATUSA.PERR).
Figure 12-2. Typical CPU Reset Extension Set and Clear Timing Diagram
12.6.3 Debugger Probe Detection
12.6.3.1 Cold-Plugging
Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU reset
extension is requested, as described above.
extension is requested, as described above.
12.6.3.2 Hot-Plugging
Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under
reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling
edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is
assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power-
reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling
edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is
assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power-
DSU CRSTEXT
Clear
SWCLK
CPU reset
extension
CPU_STATE
reset
running
RESET