Linear Technology LTC2977 Demo Board: Octal Power Supply Manager [Requires DC1613] DC2028A DC2028A Data Sheet
Product codes
DC2028A
LTC2977
30
2977fa
For more information
MFR_COMMAND_PLUS, MFR_DATA_PLUS0, MFR_DATA_PLUS1, MFR_STATUS_PLUS0, and MFR_STATUS_PLUS1
Command Plus operations use a sequence of word commands to support the following:
• An alternate method for reading block data using sequential standard word reads.
• A peek operation that allows up to two additional hosts to read an internal register using PMBus word protocol
Command Plus operations use a sequence of word commands to support the following:
• An alternate method for reading block data using sequential standard word reads.
• A peek operation that allows up to two additional hosts to read an internal register using PMBus word protocol
where each host has a unique page.
• A poke operation that allows up to two additional hosts to write an internal register using PMBus word protocol
where each host has a unique page.
• Peek, Poke and Command Plus block reads do not interfere with normal PMBus accesses or page values set by
PAGE. This enables multi master support for up to 3 hosts.
MFR_COMMAND_PLUS Data Contents
BIT(S)
SYMBOL
OPERATION
b[15]
Mfr_command_plus_
reserved
Reserved. Always returns 0.
b[14]
Mfr_command_plus_id
Command Plus host ID
0: Mfr_command_plus pointer and page are cached and used for all Mfr_data_plus0 accesses.
1: Mfr_command_plus pointer and page are cached and used for all Mfr_data_plus1 accesses.
0: Mfr_command_plus pointer and page are cached and used for all Mfr_data_plus0 accesses.
1: Mfr_command_plus pointer and page are cached and used for all Mfr_data_plus1 accesses.
b[13:9] Mfr_command_plus_page
Page to be used when peeking or poking via Mfr_data_plus0 or Mfr_data_plus1. Allowed values are 0
through 7. This page value is cached separately for Mfr_data_plus0 and Mfr_data_plus1 based on the value of
Mfr_command_plus_id when this register is written.
b[8:0]
Mfr_command_plus_pointer Internal memory location accessed by Mfr_data_plus0 or Mfr_data_plus1. Mfr_data_plus0 and Mfr_data_plus1
pointers are cached separately. Legal values are listed in the Cmd Code column of the PMBus COMMAND
SUMMARY table. All other values are reserved, except for the special poke enable/disable values listed in
and the command values listed below for Mfr_status_plus0
and Mfr_status_plus1.
MFR_DATA_PLUS0 and MFR_DATA_PLUS1 Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:0] Mfr_data_plus0
Mfr_data_plus1
A read from this register returns data referenced by the last matching Mfr_command_plus write. More
specifically, writes to Mfr_command_plus by host 0 update Mfr_data_plus0, and writes to Mfr_command_plus
by host1 update Mfr_data_plus1. Multiple sequential reads while pointer=MFR_FAULT_LOG return the complete
contents of the block read buffer. Block reads beyond the end of the buffer return zeros.
A write to this register will transfer the data to the location referenced by the last matching Mfr_command_
A write to this register will transfer the data to the location referenced by the last matching Mfr_command_
plus_pointer when the Poke operation protocol described in Poke Operation Using Mfr_data_plus0 on page
is followed.
pMbus coMManD DescripTion