Linear Technology LTC2977 Demo Board: Octal Power Supply Manager [Requires DC1613] DC2028A DC2028A Data Sheet
Product codes
DC2028A
LTC2977
49
2977fa
TOFF_DELAY = Toff_delay_master + Toff_delay_slave
Mfr_config_chan_mode = 10b
Where:
Ton_delay_master – Ton_delay_slave > RUN to TRACK setup time
Toff_delay_slave > time for master supply to fall.
The system response to a control pin toggle is illustrated in Figure 13b.
The system response to a UV fault on a slave channel is illustrated in Figure 13c.
Mfr_config_chan_mode = 10b
Where:
Ton_delay_master – Ton_delay_slave > RUN to TRACK setup time
Toff_delay_slave > time for master supply to fall.
The system response to a control pin toggle is illustrated in Figure 13b.
The system response to a UV fault on a slave channel is illustrated in Figure 13c.
MFR_CONFIG_ALL_LTC2977
This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed
This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed
from any PAGE setting.
MFR_CONFIG_ALL_LTC2977 Data Contents
BIT(S) SYMBOL
OPERATION
b[15-13] Reserved
Don’t care. Always returns 0
b[12] Mfr_config_all_en_short_cycle_fault Enable short cycle fault detection. See Mfr_status_2_short_cycle_fault on page
for more information.
0: Issuing an ON before prior OFF is complete will not cause a fault.
1: Issuing an ON before prior OFF is complete will cause a fault.
1: Issuing an ON before prior OFF is complete will cause a fault.
b[11] Mfr_config_all_pwrgd_off_uses_uv Selects PWRGD de-assertion source for all channels.
0: PWRGD is de-asserted based on V
OUT
being below or equal to POWER_GOOD_OFF. This option uses
the ADC. Response time is approximately 100ms to 200ms.
1: PWRGD is de-asserted based on V
1: PWRGD is de-asserted based on V
OUT
being below or equal to VOUT_UV_LIMIT. This option uses the
high speed supervisor. Response time is approximately 12µs
b[10] Mfr_config_all_fast_fault_log
Controls number of ADC readings completed before transferring fault log memory to EEPROM.
0: Slower. All ADC telemetry values will be updated before transferring fault log to EEPROM.
1: Faster. Telemetry values will be transferred from fault log to EEPROM within 24ms after detecting fault.
0: Slower. All ADC telemetry values will be updated before transferring fault log to EEPROM.
1: Faster. Telemetry values will be transferred from fault log to EEPROM within 24ms after detecting fault.
b[9:8] Reserved
Don’t care. Always returns 0
b[7]
Mfr_config_all_fault_log_enable
Enable fault logging to EEPROM in response to Fault.
0: Fault logging to EEPROM is disabled
1: Fault logging to EEPROM is enabled
0: Fault logging to EEPROM is disabled
1: Fault logging to EEPROM is enabled
b[6]
Mfr_config_all_vin_on_clr_faults_en Allow V
IN
rising above VIN_ON to clear all latched faults
0: VIN_ON clear faults feature is disabled
1: VIN_ON clear faults feature is enabled
1: VIN_ON clear faults feature is enabled
b[5]
Mfr_config_all_control1_pol
Selects active polarity of CONTROL1 pin.
0: Active low (pull pin low to start unit)
1: Active high (pull pin high to start unit)
0: Active low (pull pin low to start unit)
1: Active high (pull pin high to start unit)
b[4]
Mfr_config_all_control0_pol
Selects active polarity of CONTROL0 pin.
0: Active low (pull pin low to start unit)
1: Active high (pull pin high to start unit)
0: Active low (pull pin low to start unit)
1: Active high (pull pin high to start unit)
b[3]
Mfr_config_all_vin_share_enable
Allow this unit to hold SHARE_CLK pin low when V
IN
has not risen above VIN_ON or has fallen below
VIN_OFF. When enabled, this unit will also turn all channels off in response to SHARE_CLK being held low.
0: SHARE_CLK inhibit is disabled
1: SHARE_CLK inhibit is enabled
0: SHARE_CLK inhibit is disabled
1: SHARE_CLK inhibit is enabled
pMbus coMManD DescripTion