Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

Product codes
MEGA328P-XMINI
Page of 657
140
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
f
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an 
external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to 
variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and 
capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than 
f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 17-2.
Prescaler for Timer/Counter0 and Timer/Counter1
Note:
1. The synchronization logic on the input pins (
T1/T0) 
is shown in 
PSRSYNC
Clear
clk
T1
clk
T0
T1
T0
clk
I/O
Synchronization
Synchronization