Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
147
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
18.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-
inverted PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or
toggled at a compare match (See
combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-
inverted PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or
toggled at a compare match (See
18.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is
always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its
maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the
Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The
TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with
the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by
software. There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its
maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the
Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The
TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with
the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by
software. There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
18.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the
OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater
control of the compare match output frequency. It also simplifies the operation of counting external events.
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the
OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater
control of the compare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
. The counter value (TCNT2) increases until a
compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared.
Figure 18-5.
CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If
the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must
be done with care since the CTC mode does not have the double buffering feature. If the new value written to
OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will
then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match
can occur.
the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must
be done with care since the CTC mode does not have the double buffering feature. If the new value written to
OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will
then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match
can occur.
TCNTn
OCnx
(Toggle)
(Toggle)
OCnx Interrupt Flag Set
1
4
Period
2
3
(COMnx1:0 = 1)