Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

programming the BOOTRST Fuse, see 

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user 
software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the 
current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is 
executed. 

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For 
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt 
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by 
writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the 
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is 
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global 
Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global 
Interrupt Enable bit is set, and will then be executed by order of priority. 

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not 
necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the 
interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more 
instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when 
returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will 
be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following 
example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any 
pending interrupts, as shown in this example. 

Assembly Code Example

r16, SREG

; disable interrupts during timed 

sequence

EECR, EEMPE

EECR, EEPE

SREG, r16

C Code Example

char cSREG;

cSREG = SREG;

/* disable interrupts during timed sequence */

_CLI(); 

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */