Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
185
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit
detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock
recovery logic then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed
mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two
or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise
spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected,
the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock
recovery logic then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed
mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two
or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise
spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected,
the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
20.8.2 Asynchronous Data Recovery
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit
uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double
Speed mode.
uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double
Speed mode.
shows the sampling of the data bits and the parity bit. Each of the samples is given a
number that is equal to the state of the recovery unit.
Figure 20-6.
Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three
samples in the center of the received bit. The center samples are emphasized on the figure by having the
sample number inside boxes. The majority voting process is done as follows: If two or all three samples have
high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received
bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on
the RxDn pin. The recovery process is then repeated until a complete frame is received. Including the first stop
bit. Note that the Receiver only uses the first stop bit of a frame.
samples in the center of the received bit. The center samples are emphasized on the figure by having the
sample number inside boxes. The majority voting process is done as follows: If two or all three samples have
high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received
bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on
the RxDn pin. The recovery process is then repeated until a complete frame is received. Including the first stop
bit. Note that the Receiver only uses the first stop bit of a frame.
shows the sampling of the stop bit and the earliest possible beginning of the start bit of
the next frame.
Figure 20-7.
Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is
registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used
for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in
for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in
. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The early
start bit detection influences the operational range of the Receiver.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
BIT n
1
2
3
4
5
6
7
8
1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
1
2
3
4
5
6
7
8
9
10
0/1
0/1
0/1
STOP 1
1
2
3
4
5
6
0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A)
(B)
(C)