Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
206
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
• Bit 5:3 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits
must be written to zero when UCSRnC is written.
must be written to zero when UCSRnC is written.
• Bit 2 – UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is
transmitted first. Refer to the Frame Formats section page 4 for details.
transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 – UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of XCKn.
Refer to the SPI Data Modes and Timing section page 4 for details.
Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 – UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and UCPHAn bit settings
determine the timing of the data transfer. Refer to the SPI Data Modes and Timing section page 4 for details.
determine the timing of the data transfer. Refer to the SPI Data Modes and Timing section page 4 for details.
21.8.5 USART MSPIM Baud Rate Registers – UBRRnL and UBRRnH
The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation.
See
See