Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
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Product codes
MEGA328P-XMINI
219
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
Bus and generate a START condition as soon as the bus becomes free. After a START condition has been
transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see
transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see
). In
order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the
following value to TWCR:
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the
following value to TWCR:
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and
a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38.
The appropriate action to be taken for each of these status codes is detailed in
a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38.
The appropriate action to be taken for each of these status codes is detailed in
.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing
the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded,
and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following
value to TWCR:
the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded,
and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following
value to TWCR:
This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP
condition or a repeated START condition. A STOP condition is generated by writing the following value to
TWCR:
condition or a repeated START condition. A STOP condition is generated by writing the following value to
TWCR:
A REPEATED START condition is generated by writing the following value to TWCR:
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or
a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between
Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus.
a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between
Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus.
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
value
1
X
0
0
X
1
0
X
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
value
1
X
0
0
X
1
0
X
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
value
1
X
0
1
X
1
0
X
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
value
1
X
1
0
X
1
0
X
Table 22-2.
Status codes for Master Transmitter Mode
Status Code
(TWSR)
Prescaler Bits
are 0
(TWSR)
Prescaler Bits
are 0
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
and 2-wire Serial Interface
Hardware
Application Software Response
Next Action Taken by TWI Hardware
To/from TWDR
To TWCR
STA
STO
TWIN
T
TWE
A
0x08
A START condition has been
transmitted
transmitted
Load SLA+W
0
0
1
X
SLA+W will be transmitted;
ACK or NOT ACK will be received
ACK or NOT ACK will be received
0x10
A repeated START condition
has been transmitted
has been transmitted
Load SLA+W or
Load SLA+R
0
0
0
0
1
1
X
X
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
0x18
SLA+W has been transmitted;
ACK has been received
ACK has been received
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
0
1
0
0
1
0
0
1
1
1
1
1
1
1
1
X
X
X
X
X
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
0x20
SLA+W has been transmitted;
NOT ACK has been received
NOT ACK has been received
Load data byte or
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
0
1
0
0
1
0
0
1
1
1
1
1
1
1
1
X
X
X
X
X
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset